30 June – 5 July 2014 at the University of Cape Town.
The HPC Winter School is the CHPC's flagship course in parallel programming for high performance computing covering:
The CHPC is looking to distribute small compute clusters to groups that could benefit from having access to such hardware for training users in HPC basics before they need access to large clusters such as the CHPC. As part of this objective we have created 12 node clusters by breaking up racks of compute hardware that used to make up the Ranger supercomputer. This training course will cover the topics necessary for hosting a rack of Ranger hardware, such as, a hardware overview and the data-center preparation details both of which are specific to Ranger. We include a generic software stack that can be used for managing most small clusters but which has been selected as our recommendation for managing the Ranger hardware.
The CHPC has several Intel Xeon Phi co-processor cards and sees them as an essential component to achieving high performance with power efficiency. Capable of supporting 240 threads in an 8GB shared memory environment with powerful 512 bit vector arithmetic, a Phi packs 1 teraflop of HPC peformance into a single accelerator. Programming for the Phi can be challenging to incorporate all its features to achieve the maximum performance. For this reason the CHPC is hosting a dedicated programming course covering the Phi and the Intel compiler and tool chain to support development of fast HPC code.