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workshops:phi

Intel Xeon Phi Programming Course

  • When: 17 to 21 February 2014
  • Where: CHPC, Cape Town

The CHPC has several Intel Xeon Phi co-processor cards and sees them as an essential component to achieving high performance with power efficiency. Capable of supporting 240 threads in an 8GB shared memory environment with powerful 512 bit vector arithmetic, a Phi packs 1 teraflop of HPC peformance into a single accelerator. Programming for the Phi can be challenging to incorporate all its features to achieve the maximum performance. For this reason the CHPC is hosting a dedicated programming course covering the Phi and the Intel compiler and tool chain to support development of fast HPC code.

Course Outline

Introduction to Intel compilers and optimization concepts

Xeon Phi architecture deep dive:

  • executable units of the processor
  • memory subsystem
  • communication interface to the host
  • hardware threading model

Optimizing for the architecture by making use of threading and vectorization

Programming for Xeon Phi:

  • Offload model using implicit and explicit interfaces
  • Library execution
  • Native execution

Performance and parallel libraries:

  • Math kernel library
  • MPI
  • OpenMPI

Getting the most out of an application:

  • Symmetric host/device execution
  • Debugging
  • Profiling using Intel Vtune

LIMITED PLACES

There are only 15 available places in this course owing to its intensive practical focus. For this reason, we may not be able to accept all the applicants from the same group.

Prerequisites

C/C++ (or Fortran) and the Linux programming environment, compilers and tools.

Please detail your experience and skills with C/C++ and Linux in the application form.

Application Forms

  • Open Office or Libre Office ODT format file
  • MS Office DOC format file

Complete either form electronically and email the file to: workshop .AT. chpc .dot. ac .dot. za

Lecturer

Martin Hilgeman

Enterprise Technologist HPC
Dell

Martin Hilgeman joined Dell in 2011, where he is a technical lead for the HPC benchmarking group. His particular specialities are in application optimisation, accelerators, architecture considerations for task placement, MPI single-sided messaging and optimisation of collectives. Previously he worked at SGI for 11 years as a consultant and member of the technical staff in the applications engineering group, where his main involvement was in porting, optimisation and parallelisation of computational chemistry and material sciences applications for MIPS, Intel Itanium 2 and Intel em64t platforms. Martin has an advanced master's degree in Physical and Organic chemistry from the VU University of Amsterdam.

/var/www/wiki/data/pages/workshops/phi.txt · Last modified: 2014/02/07 15:37 by kevin