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Intel Xeon Phi Programming Course
- When: 17 to 21 February 2014
- Where: CHPC, Cape Town
The CHPC has several Intel Xeon Phi co-processor cards and sees them as an essential component to achieving high performance with power efficiency. Capable of supporting 240 threads in an 8GB shared memory environment with powerful 512 bit vector arithmetic, a Phi packs 1 teraflop of HPC peformance into a single accelerator. Programming for the Phi can be challenging to incorporate all its features to achieve the maximum performance. For this reason the CHPC is hosting a dedicated programming course covering the Phi and the Intel compiler and tool chain to support development of fast HPC code.
Course Outline
Introduction to Intel compilers and optimization concepts
Xeon Phi architecture deep dive:
- executable units of the processor
- memory subsystem
- communication interface to the host
- hardware threading model
Optimizing for the architecture by making use of threading and vectorization
Programming for Xeon Phi:
- Offload model using implicit and explicit interfaces
- Library execution
- Native execution
Performance and parallel libraries:
- Math kernel library
- MPI
- OpenMPI
Getting the most out of an application:
- Symmetric host/device execution
- Debugging
- Profiling using Intel Vtune
LIMITED PLACES
There are only 15 available places in this course owing to its intensive practical focus. For this reason, we may not be able to accept all the applicants from the same group.
Prerequisites
C/C++ (or Fortran) and the Linux programming environment, compilers and tools.
Please detail your experience and skills with C/C++ and Linux in the application form.
Application Forms
