• When: 17 to 21 February 2014
• Where: CHPC, Cape Town

The CHPC has several Intel Xeon Phi co-processor cards and sees them as an essential component to achieving high performance with power efficiency. Capable of supporting 240 threads in an 8GB shared memory environment with powerful 512 bit vector arithmetic, a Phi packs 1 teraflop of HPC peformance into a single accelerator. Programming for the Phi can be challenging to incorporate all its features to achieve the maximum performance. For this reason the CHPC is hosting a dedicated programming course covering the Phi and the Intel compiler and tool chain to support development of fast HPC code.

Information and application forms for Xeon Phi programming course...

2013